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Revision 34231 - Directory Listing
Modified Fri Jul 24 15:40:09 2009 UTC (2 days, 18 hours ago) by iu42
FPGA_EBPM : v2.02.3
FastFeedbackFPGA :
    * A death period of 64 clock cycles are introduced for PMC time frame start bit generation to allow TX Fifo reset.
    * RX Fifo reset on every timeframe is removed due to gliches appearing when a BPM starts walking away in phase.
    
Neutrino_EBPM :
    * No change



Revision 33832 - Directory Listing
Modified Tue Jul 21 13:50:38 2009 UTC (5 days, 20 hours ago) by iu42
FPGA_EBPM : v2.02.2
FastFeedbackFPGA :
    * On PMC: DMA handshaking start bug is fixed. It, now, happens at the rising edge of the time_frame_end signal, rather than the falling edge.
    * missed_dma_ counter reading, and DMA acknowledment are synchronised. You do not need to write to dma_ack register anymore. This used to cause occasional misreadings on the missed_dma_counter.
    * You need to read fofb_node_mask register within 100usec after the interrupt. It is not double buffered.
    * missed_dma_counter is fixed. It reads 0 (zero) when there is no dma miss.
    * It returns 0 (zero) as x&y position data for inactive BPMs on the network.

Neutrino_EBPM :
    * No change


Revision 33796 - Directory Listing
Modified Mon Jul 20 20:43:26 2009 UTC (6 days, 13 hours ago) by iu42
FPGA_EBPM:
    - PMC option is added into Makefile
FastFeedbackFPGA:
    - Time frame end bug fix in bus_ctrl_pmc.vhd module.


Revision 33658 - Directory Listing
Modified Tue Jul 14 10:18:47 2009 UTC (13 days ago) by mga83
Libera FPGA:
 * Separate version information into a VERSION file which should be easier to
   maintain correctly.
 * By default build both brilliance and electron versions, placing the 
   resulting files in the current directory.

Revision 32422 - Directory Listing
Modified Wed Jun 10 11:05:48 2009 UTC (6 weeks, 4 days ago) by mga83
Libera FPGA:
 * Add top level make file to automate build process.
 * Also add top level script to run simulation.
 * Automatically generate FPGA version from version information in new top 
   level Makefile.
 * Rewrite spike removal.  Now works correctly with average lengths other 
   than 8, and consumes about 5% fewer FPGA slices.
 * Some updates to the simulation workbench to capture spike removal issues.

Revision 31793 - Directory Listing
Modified Mon May 18 15:44:42 2009 UTC (2 months, 1 week ago) by iu42
FPGA_EBPM : v2.02.0
FastFeedbackFPGA :
    * Re-versioned to be aligned with ITech 2.02 release.

Neutrino_EBPM :
    * ITech 2.02 release merged. New build environment.
    * DLS LEDs logic, ADC overflow is added.


Revision 31407 - Directory Listing
Modified Fri May 1 14:54:14 2009 UTC (2 months, 3 weeks ago) by iu42
FPGA_EBPM : v1.70.7
    - ITECH release v2.02 with DLS CC is merged.
    - neutrino_fofb from Neutrino_EBPM/rtl/ is removed and linked to FastFeedback directory. 


Revision 31355 - Directory Listing
Modified Fri May 1 12:49:13 2009 UTC (2 months, 3 weeks ago) by iu42
FPGA_EBPM : v1.70.7
FastFeedbackFPGA : 
    * DMA watchdog counter on PMC is implemented.

Neutrino_EBPM :
    * Simulation directory added.


Revision 27770 - Directory Listing
Modified Wed Jan 28 16:10:23 2009 UTC (5 months, 3 weeks ago) by iu42
FPGA_EBPM : v1.70.6
FastFeedbackFPGA :
    * IRQ generator (pmc_irq_gen) project added targeting PMC modules. It generates Irqs at 10kHz.

Revision 25455 - Directory Listing
Modified Fri Nov 14 12:00:17 2008 UTC (8 months, 1 week ago) by iu42
FPGA_EBPM : v1.70.6
FastFeedbackFPGA : 
    * Only version increment.

Neutrino_EBPM :
    * DSC_IL_OF_MAX_VAL_REG is moved to 0x1400 C004. This was DLS epics driver can support original I-Tech design, since it also keeps writing to original address.
    * CUSTOMER_FEATURE_REG is set to 0x8000 0000. This register is used to idetify DLS modification.
    * Bit 23 of ITECH_FEATURE_REG is set to 1. This register is used to identify the DLS modified design. If set to 0, epics driver ignores DLS related features.


Revision 25282 - Directory Listing
Modified Thu Nov 13 12:29:05 2008 UTC (8 months, 1 week ago) by mga83
FPGA EBPM: Set DLS identfication bit in iTech feature register.  This may be
temporary and may end up being rolled back.

Revision 25126 - Directory Listing
Modified Tue Nov 11 13:03:05 2008 UTC (8 months, 2 weeks ago) by iu42
FPGA_EBPM : v1.70.5
    - FastFeedbackFPGA has not been modified aprat from version info incremented by 1.

Neutrino_EBPM :
    - I-Tech's ADC overflow for interlocking is removed, and dls-based overflow detection added. neutrino_dsc_overflow_dls.v is added.


Revision 19955 - Directory Listing
Modified Tue May 20 09:03:36 2008 UTC (14 months, 1 week ago) by iu42


Revision 18791 - Directory Listing
Modified Thu Apr 24 11:39:46 2008 UTC (15 months ago) by iu42
FPGA_EBPM : v1.70.4
    * Single fofb_cc_fod module is used for both bpm and pmc designs.

FPGA_EBPM_DevKit : 
    * This moudle is used for I-Tech DevKit. The fai_cfg interface is hardlinked to adc_clk in the I-Tech core, so fofb_cc_config_intf module was modified to work on adc_clk domain rather that mgt_clk domain.
        

Revision 17675 - Directory Listing
Modified Thu Mar 27 15:54:00 2008 UTC (16 months ago) by iu42
FPGA_EBPM : v1.70.2
    * fofb_node_mask (256-bit) added on pmc design to indicate all bpms status
    on the network.
    

Revision 16443 - Directory Listing
Modified Thu Feb 14 16:44:00 2008 UTC (17 months, 1 week ago) by iu42
FPGA_EBPM : v1.70.2
    * compile script for BPM compilation added in the top project directory


Revision 16400 - Directory Listing
Modified Wed Feb 13 14:40:48 2008 UTC (17 months, 1 week ago) by iu42
FPGA_EBPM : v1.70.2
    NeutrinoFPGA
        * v1.80 is integrated
        * 32-bit BRAMs are put back in fai and sa_output_buffer modules
        * Makefile need DLS_DESIGN=bpm/pmc for fofb_cc_fod module.
    FastFeedbackFPGA
        * fofb_cc_fod is re-implemented for BPMs using BRAM as a sent array. The file is renamed as fofb_cc_fod_bpm.vhd. fofb_cc_fod_pmc keeps the original implementation.
       

Revision 12856 - Directory Listing
Modified Mon Oct 22 08:39:34 2007 UTC (21 months ago) by iu42
FPGA_EBPM : v1.70.1
    FastFeedbackFPGA
        * CC specification document added under /doc


Revision 12841 - Directory Listing
Modified Fri Oct 19 08:48:24 2007 UTC (21 months, 1 week ago) by iu42
FPGA_EBPM : v1.70.1
    Neutrino_FPGA
        * Crosstalk stage in DSC is removed.
        * IIR max adc logic is removed.


Revision 12557 - Directory Listing
Modified Wed Oct 3 15:17:42 2007 UTC (21 months, 3 weeks ago) by iu42
FPGA_EBPM : v1.70.0
    FastFeedbackFPGA
        * Unused files/directories removed.
        * Code cleaned up/comments added.
    

Revision 11546 - Directory Listing
Modified Fri Aug 17 10:07:50 2007 UTC (23 months, 1 week ago) by iu42
FPGA_EBPM : v1.69.8
    Neutrino_FPGA
            * both maximum adc values (iir output & direct adc output) made accessible
            

Revision 11417 - Directory Listing
Modified Tue Aug 14 13:25:21 2007 UTC (23 months, 1 week ago) by iu42
FPGA_EBPM : v1.69.7
    Neutrino_FPGA
        * maximum adc value (iir output & direct adc output) added


Revision 11307 - Directory Listing
Modified Mon Aug 13 09:44:22 2007 UTC (23 months, 2 weeks ago) by iu42
FPGA_EBPM : v1.69.6
    FastFeedbackFPGA
        * Filter (*.dat) files added for neutrino_fa simulation.


Revision 11266 - Directory Listing
Modified Wed Aug 8 16:15:19 2007 UTC (23 months, 2 weeks ago) by iu42
FPGA_EBPM : v1.69.6
    FastFeedbackFPGA
        * Full neutrino_fa simulation added (filter loading, I&Q reading and loading, fa result in a file etc).
        

Revision 11249 - Directory Listing
Modified Tue Aug 7 15:17:41 2007 UTC (23 months, 2 weeks ago) by iu42
FPGA_EBPM : v1.69.6
    Neutrino_FPGA
        * fa data postmortem triggering added.
        * new registers are defined in Neutrino FA address space for fa pm operation.        
    FastFeedbackFPGA
        * neutrino_fa and neutrino_ddc sim directories and files added.
        

Revision 10943 - Directory Listing
Modified Thu Jul 26 13:40:16 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.69.4
    FastFeedbackFPGA
        * Testbench for mgt_interface updated (for CRC tests)
        * mgt_interface warnings cleaned
        

Revision 10886 - Directory Listing
Modified Wed Jul 25 14:54:25 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.69.4
    FastFeedbackFPGA
        * NodeNum and NodeNumIndexWidth parameters are set for Diamond configuration (it was set to Soleil)
        

Revision 10870 - Directory Listing
Modified Wed Jul 25 14:19:26 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.69.4
    Neutrino_FPGA
       * neutrino_top : fofb_cc_top module RIO ports connections are now parametrisable.
    FastFeedbackFPGA
       * fofb_cc_user_pkg  : AlreadySentBitArray made parametrisable. BpmCount and BpmIndexWidth are introduced.
       * fofb_cc_user_defs : FA_LIMITER_EN parameter introduced.
       * xy_position_array implemented using 2 18-bit BRAMs.
       * fofb_cc_frame_cntrl ports are set to 4 RIO width.


Revision 10600 - Directory Listing
Modified Wed Jul 18 10:14:53 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.69.2
    Neutrino_EBPM
        * SA data problem solved by recompiling.                    
    FastFeedbackFPGA
        * fofb_cc_max_adc module added to svn repository.
        

Revision 10538 - Directory Listing
Modified Fri Jul 13 15:37:00 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.69.0
    Neutrino_EBPM
        * fofb_cc_max_adc module instantiated in neutrino_adc_capture module
        * max adc value register @ 0x14008004 defined in neutrino_adc_capture module
    FastFeedbackFPGA
        * fofb_cc_max_adc module implemented
        

Revision 10464 - Directory Listing
Modified Wed Jul 11 16:00:17 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.68.6
    FastFeedbackFPGA
        - Time Frame Counter is changed to 32-bit
        - Missed DMA Counter is added in PMC
        

Revision 10415 - Directory Listing
Modified Mon Jul 9 08:46:11 2007 UTC (2 years ago) by iu42
FPGA_EBPM : v1.68.5
    FastFeedbackFPGA
        * v1.67.5 is copied back
        * Time Frame Counter reduced to 22-bit
        * TimeFrameCount is read from the first arriving bpm packet on PMC
        * Configuration parameters are updated when there is no data communication
        * FA_LIMITER_EN user definition added
        * DMA transfer handshaking and dobule buffer switching happen on SYS CLK domain 
        

Revision 10209 - Directory Listing
Modified Tue Jun 26 12:23:10 2007 UTC (2 years, 1 month ago) by iu42
FPGA_EBPM : v1.67.6
    FastFeedbackFPGA
        * fofb_cc_config_intf: address bus decreased to 4 bits for config registers.
        

Revision 10152 - Directory Listing
Modified Mon Jun 25 15:43:37 2007 UTC (2 years, 1 month ago) by iu42
PGA_EBPM : v1.67.6
    Neutrino_FPGA
        * neutrino_top : fofb_cc_top module RIO ports connections are now parametrisable.
    FastFeedbackFPGA
        * fofb_cc_user_pkg  : AlreadySentBitArray made parametrisable. BpmCount and BpmIndexWidth are introduced.
        * fofb_cc_user_defs : FA_LIMITER_EN parameter introduced.
        * xy_position_array implemented using 2 18-bit BRAMs.
        * fofb_cc_frame_cntrl ports are set to 4 RIO width.


Revision 10081 - Directory Listing
Modified Fri Jun 22 08:42:56 2007 UTC (2 years, 1 month ago) by iu42
FPGA_EBPM : v1.67.5
    FastFeedbackFPGA
        * Readback registers removed in fofb_cc_config file.
        * syn/fofb_cc_top branch updaded.


Revision 10010 - Directory Listing
Modified Wed Jun 20 08:46:29 2007 UTC (2 years, 1 month ago) by iu42
FPGA_EBPM : v1.67.5
    Neutrino_FPGA
        * New vendor release v1.46 has been integrated. Following files were modifed in neutrino desing by I-Techfrom v1.40 -> v1.46:
            - rtl/itech/rtl/verilog: aux_sdram_init.v (NEW file)
            - rtl/itech/rtl/verilog/dec.v
            - rtl/neutrino_defines/itech/neutrino_stamp.v
            - rtl/neutrino_top/rtl/verilog/neutrino_top.v
            - syn/neutrino_top/constr/neutrino_top.ucf
            - syn/neutrino_top/xilinx/neutrino_common.lst
            

Revision 9889 - Directory Listing
Modified Mon Jun 18 15:51:38 2007 UTC (2 years, 1 month ago) by iu42
FPGA_EBPM : v1.67.4
    FastFeedbackFPGA
        * DMA transfer acknowledgement mechanism added for PMC operation. Register @ BAR2+0x18 is used (1) to read missed frames (2) to acknowledge (on read) dma transfer completion.
        * Internal double buffers are switched on time_frame_end_rise if the previous dma transfer has been acknowledged.


Revision 9650 - Directory Listing
Modified Thu Jun 7 12:17:58 2007 UTC (2 years, 1 month ago) by iu42
FPGA_EBPM : v1.67.3
    * /syn/neutrino_dsc added for module investigation.


Revision 8204 - Directory Listing
Modified Thu Apr 5 14:11:15 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.67.3
    FastFeedbackFPGA
        * rx_pck_count is fixed.
        * time_stamp buffers are removed since there is no use.

Revision 8182 - Directory Listing
Modified Thu Apr 5 08:22:30 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.67.2
    FastFeedbackFPGA
        * bug fix for tfs_pmc_counter in frame_cntrl module.

Revision 8170 - Directory Listing
Modified Wed Apr 4 15:25:40 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.67.2
    FastFeedbackFPGA
            * frame_timout condition is back in mgt_interface.
            * tx/rx_sm_sta is back in fifo_rst.
            * a bug is fixed regarding tfs_pmc_i generation in frame_cntrl. 

Revision 8015 - Directory Listing
Modified Tue Apr 3 12:36:38 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.67.0
    FastFeedbackFPGA
        * full length check on cfg_addr in configuration interface.
        * rx_data_monitor is connected to soft_error.

Revision 7971 - Directory Listing
Modified Tue Apr 3 09:21:26 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.66.9
    FastFeedbackFPGA 
        * fofb_cc_frame_cntrl.chd re-implemented.
        * BPMs only accept internal time_frame_start and PMCs accept only start_bit from incoming packets.

Revision 7952 - Directory Listing
Modified Tue Apr 3 08:17:58 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.66.8
    FastFeedbackFPGA
        * cfg_val_mgt bug has been corrected as (3 downto 0),
        * frame_timeout is removed in mgt_interface module
        * tx/rx_sm_sta dependency on fifo_rst has been removed.

Revision 7883 - Directory Listing
Modified Mon Apr 2 13:00:16 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.66.7
    FastFeedbackFPGA:
        * 1sec heart beat for communication controller added.

Revision 7728 - Directory Listing
Modified Thu Mar 29 13:32:04 2007 UTC (2 years, 3 months ago) by iu42
FPGA_EBPM : v1.66.6
    * fofb_cc_config_intf.vhd has been re-implemented in order to remove glitches during st_write->st_read state transitions.
    * configuration parameters (bpm_id, time_frame_length etc.) readback has been implemented.
    * fai_cfg_mgt_val has been decreased to 4-bits (from 32-bits).
    * if (CRC_ENABLED) conditions are removed in fofb_cc_mgt_interface.vhd.
    * Warnings about non-assigned AND non-used signals are removed.


Revision 7574 - Directory Listing
Modified Tue Mar 27 15:55:43 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM : v1.66.5
    * WARNINGs from xst.srp have been addressed.
    * pos_data_sel interface fixed in EPICS release v1.40.1.9
       

Revision 7573 - Directory Listing
Modified Tue Mar 27 15:51:47 2007 UTC (2 years, 4 months ago) by iu42


Revision 7562 - Directory Listing
Modified Tue Mar 27 14:21:51 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM : (1) v1.66.4 ; (2) dma transfer process fixed in pmc_top.vhd (3) adc clock domain removed in pmc_top.vhd

Revision 7557 - Directory Listing
Modified Tue Mar 27 12:57:16 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM : (1) v1.66.3 ; (2) fai_cfg interface is on mgt_clk domain (3) full reset on fa_interface

Revision 7554 - Directory Listing
Modified Tue Mar 27 11:40:47 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM : (1) ROLLED BACK to revision 7450; (2) tx_reset is fixed in mgt_interface; (3) arbmux input stage fixed.

Revision 7523 - Directory Listing
Modified Mon Mar 26 14:18:25 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM (v1.66.1) : (1) fai_cfg_clk input is defined in neutrino_fai.vso that configuration interface now runs on mgt_clk rather than adc_clk; (2) Warning removal.

Revision 7500 - Directory Listing
Modified Mon Mar 26 08:54:31 2007 UTC (2 years, 4 months ago) by iu42
FGPA_EBPM (v1.66.0) : Bug removal (fofb_cc_arbmux). Has been tested on the SR.

Revision 7450 - Directory Listing
Modified Thu Mar 22 12:59:32 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM (v1.66.1) : (1) NEW fofb_cc_fod.vdh module implemented based on AlreadySentArrayBit register array. (2) fod_process_time & bpm_count status information fixed. (3) tested in the 6 lab ebpms.

Revision 7399 - Directory Listing
Modified Tue Mar 20 12:25:09 2007 UTC (2 years, 4 months ago) by iu42
FPGA_EBPM : bpm_count & process_time on pmc interface implemented. CRCs are corrected.

Revision 6328 - Directory Listing
Modified Fri Feb 16 15:23:37 2007 UTC (2 years, 5 months ago) by iu42
FPGA EBPM: v1_40 with SOLEILs modifications. Configuration space modified so that RM and Golden Orbit can be read from SBC. user_defs file is introduced.

Revision 6044 - Directory Listing
Modified Mon Feb 5 15:49:09 2007 UTC (2 years, 5 months ago) by iu42
FPGA_EBPM v1_40: FA capture is implemented as part of BPM.

Revision 5927 - Directory Listing
Modified Wed Jan 31 15:26:39 2007 UTC (2 years, 5 months ago) by iu42
FPGA_EBPM : input/output and signal naming corrected, all lower case.

Revision 5922 - Directory Listing
Modified Wed Jan 31 14:22:28 2007 UTC (2 years, 5 months ago) by jr76
fast feedback fpga: make BIT files not BIN files

Revision 5921 - Directory Listing
Modified Wed Jan 31 13:46:33 2007 UTC (2 years, 5 months ago) by jr76
fast feedback fpga: added hex2bin binary dependency and top level makefile

Revision 5918 - Directory Listing
Modified Wed Jan 31 12:11:06 2007 UTC (2 years, 5 months ago) by iu42
FPGA_EBPM: Sniffer mode of operation has been implemented. New configuration package has been defined for BPM/PMC/SNIFFER. It automatically picks up the related configuration package.

Revision 5917 - Directory Listing
Modified Wed Jan 31 11:00:02 2007 UTC (2 years, 5 months ago) by iu42
Neutrino EBPM: .ucf and .lst files are added for Booster configuration

Revision 5605 - Directory Listing
Modified Wed Jan 10 14:18:17 2007 UTC (2 years, 6 months ago) by iu42
Neutrino_EBPM: merge final local changes for version 1.40

Revision 5604 - Directory Listing
Modified Wed Jan 10 14:08:07 2007 UTC (2 years, 6 months ago) by iu42
Neutrino_EBPM: Merge vendor 1.40 release into trunk.  Initial conflicts resolved.

Revision 5601 - Directory Listing
Added Wed Jan 10 13:26:39 2007 UTC (2 years, 6 months ago) by iu42
Libera FPGA: rearrange trunk to keep Neutrino and local work together

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